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42 lines
1.2 KiB
Plaintext
42 lines
1.2 KiB
Plaintext
* Z:\home\tom\projects\LTSpice\DCC-Booster-Endstufe\Booster-LTSpice.asc
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M1 N003 N009 RAIL_A RAIL_A IPD135N03L
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M2 RAIL_A N013 0 0 IPD135N03L
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M3 RAIL_B N012 0 0 IPD135N03L
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M4 N003 N004 RAIL_B RAIL_B IPD135N03L
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V1 DCC 0 PULSE(0 5 0 200n 200n 58µ 116µ)
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R1 RAIL_B RAIL_A 2 pwr=100
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V3 N002 0 12V
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R2 N009 N008 47R
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R3 N013 N010 47R
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R4 N005 N004 47R
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R5 N007 N012 47R
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D1 N009 N008 1N4148
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D2 N013 N010 1N4148
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D3 N004 N005 1N4148
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D4 N012 N007 1N4148
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V2 N003 0 15V
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XU1 N010 N008 0 DCC N002 N006 RAIL_A N001 IR2104S
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XU3 N007 N005 0 _DCC N002 N011 RAIL_B N001 IR2104S
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D5 N002 N006 BAT54
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D6 N002 N011 BAT54
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C1 N006 RAIL_A 100n V=50 Irms=0 Rser=0.0172 Lser=1.12p
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C2 RAIL_B N011 100n V=50 Irms=0 Rser=0.0172 Lser=1.12p
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V4 N001 0 5V
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C3 RAIL_A 0 100n
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C4 RAIL_B 0 100n
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A1 DCC 0 0 0 0 _DCC 0 0 BUF Vhigh=5 Vlow=1
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.model D D
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.lib C:\users\tom\Documents\LTspiceXVII\lib\cmp\standard.dio
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.model NMOS NMOS
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.model PMOS PMOS
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.lib C:\users\tom\Documents\LTspiceXVII\lib\cmp\standard.mos
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.tran 500µs
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* Netzteil Gleisspannung
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* _SD Gate Driver Enable (Port vom Controller)
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* +12V VCC Gate Driver
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* PWM Generator 58µs / 116µs DCC Signal
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* Gleis
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.lib Z:\home\tom\projects\atmel\BJ-DCC\Documentation\LTSpice\IR2104S.lib
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.backanno
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.end
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