* Z:\home\tom\projects\LTSpice\DCC-Booster-Endstufe\Booster-LTSpice.asc
M1 N003 N009 RAIL_A RAIL_A IPD135N03L
M2 RAIL_A N013 0 0 IPD135N03L
M3 RAIL_B N012 0 0 IPD135N03L
M4 N003 N004 RAIL_B RAIL_B IPD135N03L
V1 DCC 0 PULSE(0 5 0 200n 200n 58µ 116µ)
R1 RAIL_B RAIL_A 2 pwr=100
V3 N002 0 12V
R2 N009 N008 47R
R3 N013 N010 47R
R4 N005 N004 47R
R5 N007 N012 47R
D1 N009 N008 1N4148
D2 N013 N010 1N4148
D3 N004 N005 1N4148
D4 N012 N007 1N4148
V2 N003 0 15V
XU1 N010 N008 0 DCC N002 N006 RAIL_A N001 IR2104S
XU3 N007 N005 0 _DCC N002 N011 RAIL_B N001 IR2104S
D5 N002 N006 BAT54
D6 N002 N011 BAT54
C1 N006 RAIL_A 100n V=50 Irms=0 Rser=0.0172 Lser=1.12p
C2 RAIL_B N011 100n V=50 Irms=0 Rser=0.0172 Lser=1.12p
V4 N001 0 5V
C3 RAIL_A 0 100n
C4 RAIL_B 0 100n
A1 DCC 0 0 0 0 _DCC 0 0 BUF Vhigh=5 Vlow=1
.model D D
.lib C:\users\tom\Documents\LTspiceXVII\lib\cmp\standard.dio
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\tom\Documents\LTspiceXVII\lib\cmp\standard.mos
.tran 500µs
* Netzteil Gleisspannung
* _SD Gate Driver Enable (Port vom Controller)
* +12V VCC Gate Driver
* PWM Generator 58µs / 116µs DCC Signal
* Gleis
.lib Z:\home\tom\projects\atmel\BJ-DCC\Documentation\LTSpice\IR2104S.lib
.backanno
.end