diff --git a/DCC-Booster-Endstufe/Booster-LTSpice.asc b/DCC-Booster-Endstufe/Booster-LTSpice.asc new file mode 100644 index 0000000..9fa82c4 --- /dev/null +++ b/DCC-Booster-Endstufe/Booster-LTSpice.asc @@ -0,0 +1,258 @@ +Version 4 +SHEET 1 2220 680 +WIRE -624 -576 -928 -576 +WIRE 1488 -576 -624 -576 +WIRE -464 -528 -752 -528 +WIRE 1552 -528 -464 -528 +WIRE 192 -480 96 -480 +WIRE 752 -480 192 -480 +WIRE -928 -336 -928 -576 +WIRE -752 -336 -752 -528 +WIRE 96 -336 96 -400 +WIRE -928 -176 -928 -256 +WIRE -752 -176 -752 -256 +WIRE 1024 -128 1008 -128 +WIRE 1120 -128 1088 -128 +WIRE -464 -112 -464 -528 +WIRE -384 -112 -464 -112 +WIRE -240 -112 -320 -112 +WIRE -176 -112 -240 -112 +WIRE 1008 -80 1008 -128 +WIRE 1008 -80 656 -80 +WIRE 1024 -80 1008 -80 +WIRE 1120 -80 1120 -128 +WIRE 1120 -80 1104 -80 +WIRE 1232 -80 1120 -80 +WIRE -176 -64 -176 -112 +WIRE -464 0 -464 -112 +WIRE -416 0 -464 0 +WIRE -240 0 -240 -112 +WIRE -240 0 -288 0 +WIRE 192 16 192 -480 +WIRE 752 16 752 -480 +WIRE 1264 16 1216 16 +WIRE 1456 16 1392 16 +WIRE -704 32 -768 32 +WIRE -512 32 -704 32 +WIRE -416 32 -512 32 +WIRE -96 32 -288 32 +WIRE -64 32 -96 32 +WIRE 32 32 0 32 +WIRE 1264 48 928 48 +WIRE 1488 48 1488 -576 +WIRE 1488 48 1392 48 +WIRE -624 64 -624 -576 +WIRE -416 64 -624 64 +WIRE -176 64 -176 0 +WIRE -176 64 -288 64 +WIRE 1232 80 1232 -80 +WIRE 1264 80 1232 80 +WIRE 1680 80 1392 80 +WIRE 1792 80 1680 80 +WIRE -768 96 -768 32 +WIRE -416 96 -464 96 +WIRE -224 96 -288 96 +WIRE -96 96 -96 32 +WIRE -64 96 -96 96 +WIRE 32 96 32 32 +WIRE 32 96 16 96 +WIRE 144 96 32 96 +WIRE 656 96 656 -80 +WIRE 704 96 656 96 +WIRE 1264 112 1232 112 +WIRE 1552 112 1552 -528 +WIRE 1552 112 1392 112 +WIRE 1040 144 1008 144 +WIRE 1120 144 1104 144 +WIRE -176 160 -176 64 +WIRE 192 160 192 112 +WIRE 192 160 -176 160 +WIRE 304 160 192 160 +WIRE 400 160 400 16 +WIRE 400 160 304 160 +WIRE 416 160 400 160 +WIRE 512 160 512 16 +WIRE 512 160 496 160 +WIRE 592 160 512 160 +WIRE 752 160 752 112 +WIRE 752 160 592 160 +WIRE 928 160 928 48 +WIRE 928 160 752 160 +WIRE 1008 192 1008 144 +WIRE 1008 192 656 192 +WIRE 1024 192 1008 192 +WIRE 1120 192 1120 144 +WIRE 1120 192 1104 192 +WIRE 1216 192 1216 16 +WIRE 1216 192 1120 192 +WIRE 192 224 192 160 +WIRE 400 224 400 160 +WIRE 512 224 512 160 +WIRE 752 224 752 160 +WIRE 928 224 928 160 +WIRE 1232 224 1232 112 +WIRE 1296 224 1232 224 +WIRE 1552 224 1552 112 +WIRE 1552 224 1360 224 +WIRE -64 240 -96 240 +WIRE -224 304 -224 96 +WIRE -96 304 -96 240 +WIRE -96 304 -224 304 +WIRE -80 304 -96 304 +WIRE 16 304 16 240 +WIRE 16 304 -16 304 +WIRE 144 304 16 304 +WIRE 656 304 656 192 +WIRE 704 304 656 304 +WIRE 928 320 928 288 +WIRE 1232 320 1232 224 +WIRE 1232 320 928 320 +WIRE -768 384 -768 176 +WIRE -464 384 -464 96 +WIRE 192 384 192 320 +WIRE 400 384 400 288 +WIRE 512 384 512 288 +WIRE 752 384 752 320 +WIRE 1456 384 1456 16 +WIRE -512 480 -512 32 +WIRE -320 480 -512 480 +WIRE 1792 480 1792 80 +WIRE 1792 480 -256 480 +WIRE -320 544 -320 496 +FLAG 192 384 0 +FLAG 752 384 0 +FLAG -464 384 0 +FLAG -768 384 0 +FLAG -752 -176 0 +FLAG 304 160 RAIL_A +FLAG 96 -336 0 +FLAG 592 160 RAIL_B +FLAG 1456 384 0 +FLAG -928 -176 0 +FLAG 400 384 0 +FLAG 512 384 0 +FLAG -320 544 0 +FLAG -704 32 DCC +FLAG 1680 80 _DCC +SYMBOL nmos 144 16 R0 +SYMATTR InstName M1 +SYMATTR Value IPD135N03L +SYMBOL nmos 144 224 R0 +SYMATTR InstName M2 +SYMATTR Value IPD135N03L +SYMBOL nmos 704 224 R0 +SYMATTR InstName M3 +SYMATTR Value IPD135N03L +SYMBOL nmos 704 16 R0 +SYMATTR InstName M4 +SYMATTR Value IPD135N03L +SYMBOL voltage -768 80 R0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +WINDOW 3 -169 344 Left 2 +SYMATTR InstName V1 +SYMATTR Value PULSE(0 5 0 200n 200n 58µ 116µ) +SYMBOL res 512 144 R90 +WINDOW 0 0 56 VBottom 2 +WINDOW 3 32 56 VTop 2 +SYMATTR InstName R1 +SYMATTR Value 5 +SYMATTR SpiceLine pwr=100 +SYMBOL voltage -752 -352 R0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V3 +SYMATTR Value 12V +SYMBOL res 32 80 R90 +WINDOW 0 57 93 VBottom 2 +WINDOW 3 30 41 VTop 2 +SYMATTR InstName R2 +SYMATTR Value 47R +SYMBOL res 32 224 R90 +WINDOW 0 0 77 VBottom 2 +WINDOW 3 -26 19 VTop 2 +SYMATTR InstName R3 +SYMATTR Value 47R +SYMBOL res 1120 -96 R90 +WINDOW 0 59 94 VBottom 2 +WINDOW 3 31 45 VTop 2 +SYMATTR InstName R4 +SYMATTR Value 47R +SYMBOL res 1120 176 R90 +WINDOW 0 66 78 VBottom 2 +WINDOW 3 40 23 VTop 2 +SYMATTR InstName R5 +SYMATTR Value 47R +SYMBOL diode 0 16 R90 +WINDOW 0 0 32 VBottom 2 +WINDOW 3 31 37 VTop 2 +SYMATTR InstName D1 +SYMATTR Value 1N4148 +SYMBOL diode -16 288 R90 +WINDOW 0 0 32 VBottom 2 +WINDOW 3 32 32 VTop 2 +SYMATTR InstName D2 +SYMATTR Value 1N4148 +SYMBOL diode 1024 -112 R270 +WINDOW 0 32 32 VTop 2 +WINDOW 3 59 97 VBottom 2 +SYMATTR InstName D3 +SYMATTR Value 1N4148 +SYMBOL diode 1040 160 R270 +WINDOW 0 36 5 VTop 2 +WINDOW 3 63 72 VBottom 2 +SYMATTR InstName D4 +SYMATTR Value 1N4148 +SYMBOL voltage 96 -496 R0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +WINDOW 0 37 55 Left 2 +SYMATTR InstName V2 +SYMATTR Value 15V +SYMBOL AutoGenerated\\IR2104S -352 48 R0 +SYMATTR InstName U1 +SYMBOL AutoGenerated\\IR2104S 1328 64 R180 +SYMATTR InstName U3 +SYMBOL schottky -384 -96 R270 +WINDOW 0 32 32 VTop 2 +WINDOW 3 0 32 VBottom 2 +SYMATTR InstName D5 +SYMATTR Value BAT54 +SYMATTR Description Diode +SYMATTR Type diode +SYMBOL schottky 1360 208 R90 +WINDOW 0 0 32 VBottom 2 +WINDOW 3 32 32 VTop 2 +SYMATTR InstName D6 +SYMATTR Value BAT54 +SYMATTR Description Diode +SYMATTR Type diode +SYMBOL cap -192 -64 R0 +SYMATTR InstName C1 +SYMATTR Value 100n +SYMATTR SpiceLine V=50 Irms=0 Rser=0.0172 Lser=1.12p +SYMBOL cap 912 224 R0 +SYMATTR InstName C2 +SYMATTR Value 100n +SYMATTR SpiceLine V=50 Irms=0 Rser=0.0172 Lser=1.12p +SYMBOL voltage -928 -352 R0 +WINDOW 123 0 0 Left 0 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V4 +SYMATTR Value 5V +SYMBOL cap 384 224 R0 +SYMATTR InstName C3 +SYMATTR Value 100n +SYMBOL cap 496 224 R0 +SYMATTR InstName C4 +SYMATTR Value 100n +SYMBOL Digital\\inv -320 416 R0 +WINDOW 3 12 105 Left 2 +SYMATTR InstName A1 +SYMATTR Value Vhigh=5 Vlow=1 +TEXT -936 456 Left 2 !.tran 500µs +TEXT -184 -400 Left 2 ;Netzteil Gleisspannung +TEXT -920 -592 Left 2 ;_SD Gate Driver Enable (Port vom Controller) +TEXT -440 -544 Left 2 ;+12V VCC Gate Driver +TEXT -1008 496 Left 2 ;PWM Generator 58µs / 116µs DCC Signal +TEXT 408 40 Left 4 ;Gleis diff --git a/DCC-Booster-Endstufe/Booster-LTSpice.log b/DCC-Booster-Endstufe/Booster-LTSpice.log new file mode 100644 index 0000000..ee082af --- /dev/null +++ b/DCC-Booster-Endstufe/Booster-LTSpice.log @@ -0,0 +1,91 @@ +Circuit: * Z:\home\tom\projects\LTSpice\DCC-Booster-Endstufe\Booster-LTSpice.asc + +C2: Increased Cpar to 1e-013 +C1: Increased Cpar to 1e-013 +Instance "m:u3:_gd_template:_lo_stage:_lo_nmos": Length shorter than recommended for a level 1 MOSFET. +Instance "m:u3:_gd_template:_lo_stage:_lo_pmos": Length shorter than recommended for a level 1 MOSFET. +Instance "m:u3:_gd_template:_ho_stage:_ho_nmos": Length shorter than recommended for a level 1 MOSFET. +Instance "m:u3:_gd_template:_ho_stage:_ho_pmos": Length shorter than recommended for a level 1 MOSFET. +Instance "m:u1:_gd_template:_lo_stage:_lo_nmos": Length shorter than recommended for a level 1 MOSFET. +Instance "m:u1:_gd_template:_lo_stage:_lo_pmos": Length shorter than recommended for a level 1 MOSFET. +Instance "m:u1:_gd_template:_ho_stage:_ho_nmos": Length shorter than recommended for a level 1 MOSFET. +Instance "m:u1:_gd_template:_ho_stage:_ho_pmos": Length shorter than recommended for a level 1 MOSFET. +Direct Newton iteration failed to find .op point. (Use ".option noopiter" to skip.) +Starting Gmin stepping +Gmin = 10 +Gmin = 1.07374 +vernier = 0.5 +vernier = 0.25 +vernier = 0.125 +vernier = 0.0625 +Gmin = 0.995033 +vernier = 0.03125 +vernier = 0.015625 +vernier = 0.0078125 +vernier = 0.00390625 +Gmin = 1.00079 +vernier = 0.00195313 +vernier = 0.000976563 +vernier = 0.000488281 +Gmin = 0 +Gmin = 0 +Gmin stepping failed + +Starting source stepping with srcstepmethod=0 +Source Step = 3.0303% +Source Step = 33.3333% +Source Step = 50.1894% +vernier = 0.015625 +Source Step = 50.0237% +Starting source stepping with srcstepmethod=1 +Source Step = 3.0303% +Source Step = 33.3333% +Source Step = 50.1894% +vernier = 0.015625 +Source stepping failed + +Pseudo Transient failed in finding the operating point at 5.625 µs. +Trouble finding operating point....skipping operating point for Transient analysis. +Changing Tseed to 4.88281e-010 +Changing Tseed to 4.88281e-012 +Changing Tseed to 4.88281e-009 +Changing Tseed to 4.88281e-013 +Changing Tseed to 4.88281e-008 +Changing Tseed to 4.88281e-014 +to 5.49316e-014 +Heightened Def Con from 7.97822e-007 to 7.98697e-007 +Heightened Def Con from 5.85043e-005 to 5.85062e-005 +Heightened Def Con from 5.9027e-005 to 5.90278e-005 +Heightened Def Con from 0.000116278 to 0.000116279 +Heightened Def Con from 0.000116796 to 0.000116797 +Heightened Def Con from 0.000174513 to 0.000174515 +Heightened Def Con from 0.000175037 to 0.000175038 +Heightened Def Con from 0.000232265 to 0.000232266 +Heightened Def Con from 0.000232786 to 0.000232787 +Heightened Def Con from 0.000290519 to 0.000290521 +Heightened Def Con from 0.000291036 to 0.000291036 +Heightened Def Con from 0.000348263 to 0.000348264 +Heightened Def Con from 0.000348768 to 0.000348769 +Heightened Def Con from 0.000406519 to 0.000406521 +Heightened Def Con from 0.000407043 to 0.000407043 +Heightened Def Con from 0.000464275 to 0.000464276 +Heightened Def Con from 0.000464794 to 0.000464795 + +Date: Sun Mar 26 11:18:34 2023 +Total elapsed time: 4.092 seconds. + +tnom = 27 +temp = 27 +method = modified trap +totiter = 49817 +traniter = 31481 +tranpoints = 9771 +accept = 6953 +rejected = 3198 +matrix size = 577 +fillins = 267 +solver = Normal +Thread vector: 29.7/13.5[16] 8.0/2.5[16] 21.1/3.2[16] 0.9/1.5[1] 2592/500 +Matrix Compiler1: 30.76 KB object code size 5.9/3.1/[1.5] +Matrix Compiler2: 41.67 KB object code size 3.2/5.3/[1.4] + diff --git a/DCC-Booster-Endstufe/Booster-LTSpice.net b/DCC-Booster-Endstufe/Booster-LTSpice.net new file mode 100644 index 0000000..e3df9eb --- /dev/null +++ b/DCC-Booster-Endstufe/Booster-LTSpice.net @@ -0,0 +1,41 @@ +* Z:\home\tom\projects\LTSpice\DCC-Booster-Endstufe\Booster-LTSpice.asc +M1 N003 N009 RAIL_A RAIL_A IPD135N03L +M2 RAIL_A N013 0 0 IPD135N03L +M3 RAIL_B N012 0 0 IPD135N03L +M4 N003 N004 RAIL_B RAIL_B IPD135N03L +V1 DCC 0 PULSE(0 5 0 200n 200n 58µ 116µ) +R1 RAIL_B RAIL_A 2 pwr=100 +V3 N002 0 12V +R2 N009 N008 47R +R3 N013 N010 47R +R4 N005 N004 47R +R5 N007 N012 47R +D1 N009 N008 1N4148 +D2 N013 N010 1N4148 +D3 N004 N005 1N4148 +D4 N012 N007 1N4148 +V2 N003 0 15V +XU1 N010 N008 0 DCC N002 N006 RAIL_A N001 IR2104S +XU3 N007 N005 0 _DCC N002 N011 RAIL_B N001 IR2104S +D5 N002 N006 BAT54 +D6 N002 N011 BAT54 +C1 N006 RAIL_A 100n V=50 Irms=0 Rser=0.0172 Lser=1.12p +C2 RAIL_B N011 100n V=50 Irms=0 Rser=0.0172 Lser=1.12p +V4 N001 0 5V +C3 RAIL_A 0 100n +C4 RAIL_B 0 100n +A1 DCC 0 0 0 0 _DCC 0 0 BUF Vhigh=5 Vlow=1 +.model D D +.lib C:\users\tom\Documents\LTspiceXVII\lib\cmp\standard.dio +.model NMOS NMOS +.model PMOS PMOS +.lib C:\users\tom\Documents\LTspiceXVII\lib\cmp\standard.mos +.tran 500µs +* Netzteil Gleisspannung +* _SD Gate Driver Enable (Port vom Controller) +* +12V VCC Gate Driver +* PWM Generator 58µs / 116µs DCC Signal +* Gleis +.lib Z:\home\tom\projects\atmel\BJ-DCC\Documentation\LTSpice\IR2104S.lib +.backanno +.end diff --git a/DCC-Booster-Endstufe/Booster-LTSpice.plt b/DCC-Booster-Endstufe/Booster-LTSpice.plt new file mode 100644 index 0000000..a4c5833 Binary files /dev/null and b/DCC-Booster-Endstufe/Booster-LTSpice.plt differ diff --git a/DCC-Booster-Endstufe/Booster-LTSpice.raw b/DCC-Booster-Endstufe/Booster-LTSpice.raw new file mode 100644 index 0000000..5adc79e Binary files /dev/null and b/DCC-Booster-Endstufe/Booster-LTSpice.raw differ diff --git a/DCC-Booster-Endstufe/IR2104S.asy b/DCC-Booster-Endstufe/IR2104S.asy new file mode 100644 index 0000000..2009470 --- /dev/null +++ b/DCC-Booster-Endstufe/IR2104S.asy @@ -0,0 +1,32 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal -64 -72 64 72 +WINDOW 0 0 -72 Bottom 2 +WINDOW 3 0 72 Top 2 +SYMATTR Prefix X +SYMATTR Value IR2104S +SYMATTR ModelFile Z:\home\tom\projects\atmel\BJ-DCC\Documentation\LTSpice\IR2104S.lib +PIN 64 48 RIGHT 8 +PINATTR PinName LO +PINATTR SpiceOrder 1 +PIN 64 -16 RIGHT 8 +PINATTR PinName HO +PINATTR SpiceOrder 2 +PIN -64 48 LEFT 8 +PINATTR PinName COM +PINATTR SpiceOrder 3 +PIN -64 -16 LEFT 8 +PINATTR PinName IN +PINATTR SpiceOrder 4 +PIN -64 -48 LEFT 8 +PINATTR PinName VCC +PINATTR SpiceOrder 5 +PIN 64 -48 RIGHT 8 +PINATTR PinName VB +PINATTR SpiceOrder 6 +PIN 64 16 RIGHT 8 +PINATTR PinName VS +PINATTR SpiceOrder 7 +PIN -64 16 LEFT 8 +PINATTR PinName NSD +PINATTR SpiceOrder 8 diff --git a/DCC-Booster-Endstufe/IR2104S.lib b/DCC-Booster-Endstufe/IR2104S.lib new file mode 100644 index 0000000..e71d67d --- /dev/null +++ b/DCC-Booster-Endstufe/IR2104S.lib @@ -0,0 +1,341 @@ +****************************************************************************** +* Simulation model of IR2104S Level 1 for SIMetrix version 8.3g or higher +* Version: 01.00 (Revision: 138) +* (C) Copyright 2020 Infineon Technologies. All rights reserved. +* +****************************************************************************** +* Model performance : +* - Static Electrical Characteristics and Dynamic Electrical Characteristics +* are modeled with the typical values from the datasheet. +* - Temperature effects are not modeled +* +* The following features have been modeled : +* - Switching Characteristics such as propagation delay, peak currents +* - Undervoltage lockout +* +****************************************************************************** +* PINS: +* -------------------------------------------------------------------------- +* | NAME | DESCRIPTION +* -------------------------------------------------------------------------- +* | LO | Low side gate drive output +* -------------------------------------------------------------------------- +* | HO | High side gate drive output +* -------------------------------------------------------------------------- +* | COM | Low side return +* -------------------------------------------------------------------------- +* | IN | Logic input for gate driver output (HO), in phase with HO +* -------------------------------------------------------------------------- +* | VCC | Low-side and logic supply voltage +* -------------------------------------------------------------------------- +* | VB | High side floating supply +* -------------------------------------------------------------------------- +* | VS | High side floating supply return +* -------------------------------------------------------------------------- +* | NSD | Logic input for shut down, out of phase +* -------------------------------------------------------------------------- +* +****************************************************************************** +* DISCLAIMER +* +* INFINEON’S MODEL TERMS OF USE +* +* BY DOWNLOADING AND/OR USING THIS INFINEON MODEL (“MODEL”), THE USER +* (INCLUDING YOU) AGREES TO BE BOUND BY THE TERMS OF USE HERE STATED. IF USER +* DOES NOT AGREE TO ALL TERMS OF USE HERE STATED, USER SHALL NOT DOWNLOAD, +* USE OR COPY THE MODEL BUT IMMEDIATELY DELETE IT (TO THE EXTENT THAT IT +* WAS DOWNLOADED ALREADY). +* +* 1. SCOPE OF USE +* 1.1 Any use of this Model provided by Infineon Technologies AG is subject +* to these Terms of Use. +* 1.2 This Model, provided by Infineon, does not fully represent all of the +* specifications and operating characteristics of the product to which +* this Model relates. +* 1.3 This Model only describes the characteristics of a typical product. +* In all cases, the current data sheet information for a given product +* is the final design guideline and the only actual performance +* specification. Although this Model can be a useful tool to evaluate +* the product performance, it cannot simulate the exact product performance +* under all conditions and it is also not intended to replace +* bread-boarding for final verification. +* +* 2. IMPORTANT NOTICE +* 2.1 Infineon Technologies AG (“Infineon”) is not and cannot be aware of the +* specific application of the Infineon’s Model by User. However, Model may +* from time to time be used by User in potentially harmful and/or life- +* endangering applications such as traffic, logistic, medical, nuclear +* or military applications or in other applications where failure of the +* Model may predictably cause damage to persons’ life or health or to +* property (hereinafter "Critical Applications"). +* 2.2 User acknowledges that Infineon has not specifically designed or +* qualified the Model for Critical Applications that the Model may contain +* errors and bugs and that User is required to qualify the Model for +* Critical Applications pursuant to the applicable local quality, safety +* and legal requirements before permitting or giving access to any such use. +* +* 3. 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EXPORT REGULATIONS +* The User shall comply with all applicable national and international +* laws and regulations, in particular the applicable export control +* regulations and sanction programs. The User also agrees not to +* export, re-export or transfer any software or technology developed +* with or using information, software or technology offered by Infineon, +* in violation of any applicable laws or regulations of the competent +* authorities. Further, the User shall neither use any products, +* information, software and technology offered by Infineon in or in +* connection with nuclear technology or weapons of mass destruction +* (nuclear, biological or chemical) and carriers thereof nor supply +* military consignees. +* +* 7. TERMINATION OF USE PERMIT +* If the User violates these Terms of Use, such User’s permit to use +* this Model terminates automatically. In addition, Infineon may +* terminate the User’s permit to use this Model at its discretion and +* at any time regardless of any violation of these Terms of Use. In +* any of the foregoing events, the User is obliged to immediately destroy +* any content that has been downloaded or printed from Infineon’s website. +* +* 8. MISCELLANEOUS +* 8.1 These Terms of Use are subject to the laws of the Federal Republic +* of Germany with the exception of the United Nations on Purchase +* Contracts on the International Sale of Goods dated April 11, 1980 (CISG). +* The exclusive place of jurisdiction is Munich, Germany. +* 8.2 Should any provision in these Terms of Use be or become invalid, the +* validity of all other provisions or agreements shall remain unaffected +* thereby. +* +****************************************************************************** +.SUBCKT IR2104S LO HO COM IN VCC VB VS NSD +R_IN IN COM 1E12 +C_IN IN COM 1F +R_HO HO VS 1E12 +R_LO LO COM 1E12 +R_VB VB VS 1E12 +R_VCC VCC COM 1E12 +R_VS VS COM 1E12 +R_SD NSD COM 1666666.6666666665 +R_DT DT COM 1M +C_DT DT COM 1P +X_GD_TEMPLATE LO HO COM IN IN VCC VB VS NSD DT IR2104S_GD_TEMPLATE +.ENDS IR2104S +.SUBCKT IR2104S_GD_TEMPLATE LO HO COM LIN HIN VCC VB VS SD DT PARAMS: HB_EN=1 SHT_EN=1 P_OFFSET_DT=5.096849593495934E-07 P_SLOPE_DT= ++ -0.0 P_SD_D=2.2714285714285714E-08 P_TH_SD_UP=3.2 P_TH_SD_DW=0.6 P_C_SD_LPF=1.4476482730108395E-10 P_C_TPD=4.9229E-08 P_TH_TPD= ++ 0.7449688071 P_C_PW_MIN=1E-10 P_TH_HIN_OFF=0.6 P_TH_LIN_OFF=0.6 P_TH_HIN_ON=3.2 P_TH_LIN_ON=3.2 P_R_HIN_CL=1666666.6666666665 ++ P_R_LIN_CL=16666666.666666668 P_C_GATE=1E-12 P_RBOND_NMOS=0.01 P_RBOND_PMOS=0.01 P_LO_VGS_NMOS=6.5 P_LO_VGS_PMOS=6.3 P_LPMOS_LAMDA= ++ 0.161 P_LPMOS_KP=5E-06 P_LNMOS_LAMDA=0.081 P_LNMOS_KP=1.1E-05 P_HO_VGS_NMOS=6.5 P_HO_VGS_PMOS=6.3 P_HPMOS_LAMDA=0.161 P_HPMOS_KP= ++ 5E-06 P_HNMOS_LAMDA=0.081 P_HNMOS_KP=1.1E-05 P_VCC_UVH=8.9 P_VCC_UVL=8.2 P_VB_UVL=8.2 P_VB_UVH=8.9 P_R_UV_D_H=1428.5714285714287 ++ P_R_UV_D_L=1428.5714285714287 P_VCC_MIN=10 P_IQ_VCC_MIN=0.0001 P_VB_MIN=10 P_IQ_VB_MIN=2E-05 P_VCC_MAX=20 P_IQ_VCC_MAX=0.0002 ++ P_VB_MAX=20 P_IQ_VB_MAX=4E-05 P_V_LEAK=600 P_I_LEAK=1E-06 P_R_BSD=35 P_N_BSD=1.4534194248417849 P_IS_BSD=9.1E-16 +E_INT_VCC INT_VCC COM VALUE {V(VCC)} +R_INT_VCC INT_VCC COM 1E12 +C_INT_VCC INT_VCC COM 10P +G_INT_VCC VCC COM VALUE {-I(E_INT_VCC)} +R_HIN_CLAMP HIN COM {P_R_HIN_CL} +X_HIN_VCC_D HIN VCC IR2104S_ESD_DIO PARAMS: P_V_BV=0.3 P_I_BV=1M +X_COM_HIN_D COM HIN IR2104S_ESD_DIO PARAMS: P_V_BV=0.3 P_I_BV=1M +X_LIN_VCC_D LIN VCC IR2104S_ESD_DIO PARAMS: P_V_BV=0.3 P_I_BV=1M +X_COM_LIN_D COM LIN IR2104S_ESD_DIO PARAMS: P_V_BV=0.3 P_I_BV=1M +X_SD_VCC_D SD VCC IR2104S_ESD_DIO PARAMS: P_V_BV=0.3 P_I_BV=1M +X_COM_SD_D COM SD IR2104S_ESD_DIO PARAMS: P_V_BV=0.3 P_I_BV=1M +X_CL_VCC VCC COM IR2104S_CL_DIO PARAMS: P_V_BV=25 P_I_BV=1 +X_CL_VB VB VS IR2104S_CL_DIO PARAMS: P_V_BV=25 P_I_BV=1 +X_INPUT_STAGE LIN_DD HIN_DD SD_DD LIN HIN SD COM IR2104S_INPUT_STAGE PARAMS: P_SD_D={P_SD_D} P_TH_SD_UP={P_TH_SD_UP} P_TH_SD_DW= ++ {P_TH_SD_DW} P_C_SD_LPF={P_C_SD_LPF} P_C_TPD={P_C_TPD} P_TH_TPD={P_TH_TPD} P_C_PW_MIN={P_C_PW_MIN} P_TH_HIN_OFF={P_TH_HIN_OFF} ++ P_TH_LIN_OFF={P_TH_LIN_OFF} P_TH_HIN_ON={P_TH_HIN_ON} P_TH_LIN_ON={P_TH_LIN_ON} +X_DEADTIME LIN_DT_DIG HIN_DT_DIG LIN_DD HIN_DD DT VCC COM SD_DD VCC_UV IR2104S_DEADTIME PARAMS: P_SLOPE_DT={P_SLOPE_DT} P_OFFSET_DT= ++ {P_OFFSET_DT} HB_EN={HB_EN} SHT_EN = {SHT_EN} +X_HO_STAGE HO HIN_DT_DIG VCC_UV VB_UV SD_DD VB VS IR2104S_HO_STAGE PARAMS: P_RBOND_PMOS={P_RBOND_PMOS} P_RBOND_NMOS={P_RBOND_NMOS} ++ P_C_GATE={P_C_GATE} P_HO_VGS_PMOS={P_HO_VGS_PMOS} P_HPMOS_LAMDA={P_HPMOS_LAMDA} P_HPMOS_KP={P_HPMOS_KP} P_HO_VGS_NMOS= ++ {P_HO_VGS_NMOS} P_HNMOS_LAMDA={P_HNMOS_LAMDA} P_HNMOS_KP={P_HNMOS_KP} +X_LO_STAGE LO LIN_DT_DIG VCC_UV SD_DD VCC COM IR2104S_LO_STAGE PARAMS: P_RBOND_PMOS={P_RBOND_PMOS} P_RBOND_NMOS={P_RBOND_NMOS} ++ P_C_GATE={P_C_GATE} P_LO_VGS_PMOS={P_LO_VGS_PMOS} P_LPMOS_LAMDA={P_LPMOS_LAMDA} P_LPMOS_KP={P_LPMOS_KP} P_LO_VGS_NMOS= ++ {P_LO_VGS_NMOS} P_LNMOS_LAMDA={P_LNMOS_LAMDA} P_LNMOS_KP={P_LNMOS_KP} +X_UV_DETECT VCC_UV VB_UV VCC VB COM VS IR2104S_UV_DETECT PARAMS: P_VB_UVL={P_VB_UVL} P_VB_UVH={P_VB_UVH} P_R_UV_D_H={P_R_UV_D_H} ++ P_VCC_UVL={P_VCC_UVL} P_VCC_UVH={P_VCC_UVH} P_R_UV_D_L={P_R_UV_D_L} +X_CC_EMULATOR VCC COM VB VS IR2104S_CC_EMULATOR PARAMS: P_VB_MIN={P_VB_MIN} P_VCC_MIN={P_VCC_MIN} P_IQ_VB_MIN={P_IQ_VB_MIN} ++ P_IQ_VCC_MIN={P_IQ_VCC_MIN} P_I_LEAK={P_I_LEAK} P_V_LEAK={P_V_LEAK} P_VB_MAX={P_VB_MAX} P_VCC_MAX={P_VCC_MAX} P_IQ_VB_MAX= ++ {P_IQ_VB_MAX} P_IQ_VCC_MAX={P_IQ_VCC_MAX} +.ENDS IR2104S_GD_TEMPLATE +.SUBCKT IR2104S_INPUT_STAGE LIN_DD HIN_DD SD_DD LIN HIN SD COM PARAMS: P_SD_D=5E-08 P_TH_SD_UP=2.1 P_TH_SD_DW=1.1 P_C_TPD=1.9E-07 ++ P_TH_TPD=10E-9 P_TH_HIN_OFF=0.9 P_TH_LIN_OFF=0.9 P_TH_HIN_ON=2.1 P_TH_LIN_ON=2.1 P_C_PW_MIN=42E-9 P_C_SD_LPF=1E-9 +X_SD_TH SD SD_DIG COM IR2104S_STP_IDEAL PARAMS: P_TH_UP={P_TH_SD_UP} P_TH_DW={P_TH_SD_DW} +X_SD_LPF SD_DIG SD_LPF_DIG IR2104S_ADV_FILTER PARAMS: P_C_DELAY = {P_C_SD_LPF} +X_SD_DD SD_LPF_DIG SD_DD IR2104S_RC_DELAY_10 PARAMS: P_C_DELAY = {P_SD_D} +X_HIN_TH HIN HIN_DIG COM IR2104S_STP_IDEAL PARAMS: P_TH_UP={P_TH_HIN_ON} P_TH_DW={P_TH_HIN_OFF} +X_HIN_LPF HIN_DIG HIN_LPF_DIG IR2104S_ADV_FILTER PARAMS: P_C_DELAY = {P_C_PW_MIN} +X_HIN_DD HIN_LPF_DIG HIN_DD IR2104S_RC_DELAY_10 PARAMS: P_C_DELAY = {P_C_TPD} P_TH_TPD = {P_TH_TPD} +X_LIN_TH LIN LIN_DIG COM IR2104S_STN_IDEAL PARAMS: P_TH_UP={P_TH_LIN_ON} P_TH_DW={P_TH_LIN_OFF} +X_LIN_LPF LIN_DIG LIN_LPF_DIG IR2104S_ADV_FILTER PARAMS: P_C_DELAY = {P_C_PW_MIN} +X_LIN_DD LIN_LPF_DIG LIN_DD IR2104S_RC_DELAY_10 PARAMS: P_C_DELAY = {P_C_TPD} P_TH_TPD = {P_TH_TPD} +.ENDS IR2104S_INPUT_STAGE +.SUBCKT IR2104S_OVC_DETECT ITRIP RFE OVC_OUT_CTRL VCC_UV COM PARAMS: P_TH_OVC_UP=0.445 P_TH_OVC_DW=0.375 P_C_ITRIP_LPF=330E-9 ++ P_I_TRIP=2.8E-06 P_TH_RFE_UP=5.2 P_TH_RFE_DW=3.2 P_R_RFE_ON=45 P_C_ITRIP_TO_RFE=1E-9 P_C_ITRIP_TO_OUT=1E-9 P_TH_TPD_ITRIP_TO_RFE=0 +R_ITRIP ITRIP COM 800K +X_ITRIP ITRIP OVC_DIG COM IR2104S_STP_IDEAL PARAMS: P_TH_UP={P_TH_OVC_UP} P_TH_DW={P_TH_OVC_DW} +X_OVC_LPF OVC_DIG OVC_LPF_DIG IR2104S_ADV_FILTER PARAMS: P_C_DELAY = {P_C_ITRIP_LPF} +X_ITRIP_TO_RFE OVC_LPF_DIG RFE_CTRL1 IR2104S_RC_DELAY_10 PARAMS: P_C_DELAY = {P_C_ITRIP_TO_RFE} P_TH_TPD={P_TH_TPD_ITRIP_TO_RFE} +X_ITRIP_TO_OUT OVC_LPF_DIG OVC_DD IR2104S_RC_DELAY_10 PARAMS: P_C_DELAY = {P_C_ITRIP_TO_OUT} +G_RFE RFE COM VALUE {(V(RFE,COM)/{P_R_RFE_ON})*V(RFE_CTRL)} +X_RFE_TH RFE RFE_DIG COM IR2104S_STP_IDEAL PARAMS: P_TH_UP={P_TH_RFE_UP} P_TH_DW={P_TH_RFE_DW} +E_OVC_PLS OVC_PLS 0 VALUE={IF( (V(OVC_DD) > 0.5) | (V(OVC) > 0.5) , 1.0 , 0.0)} +E_OVC OVC 0 VALUE={IF( (V(OVC_PLS) > 0.5) & (V(RFE_DIG) < 0.5) , 1.0 , 0.0)} +E_OUT_CTRL OVC_OUT_CTRL 0 VALUE={V(OVC)} +E_RFE_CTRL RFE_CTRL 0 VALUE={IF( (V(VCC_UV) < 0.5) | (V(RFE_CTRL1) > 0.5) , 1.0 , 0.0 )} +.ENDS IR2104S_OVC_DETECT +.SUBCKT IR2104S_DEADTIME LIN_DT_DIG HIN_DT_DIG LIN HIN DT VCC COM SD_DD VCC_UV PARAMS: HB_EN=1 SHT_EN=0.0 P_SLOPE_DT=2.43236451E-05 ++ P_OFFSET_DT=5.4E-07 P_I_DT=1E-06 P_C_DT=10P P_TH_UP=0.5 +X_LIN_DT LIN LIN_DD IR2104S_RC_DELAY_10 PARAMS: P_C_DELAY = 0.3N +X_HIN_DT HIN HIN_DD IR2104S_RC_DELAY_10 PARAMS: P_C_DELAY = 0.1N +E_VCC_1V VCC_1V 0 VALUE={TABLE( V(VCC,COM) , 0,0 , 3,0 , 6,1 )} +G_DT VCC DT VALUE={TABLE( V(VCC,DT) , 0,0 , 10M,{P_I_DT} )} +E_HDT_PLS HIN_DT_PLS 0 VALUE={IF( ((V(HIN_DD) - V(LIN_DD)) > 0.1) | (V(HIN_DT_DIG) > 0.5) | ({HB_EN} < 0.5), 1.0 , 0.0 )} +E_HIN_DT HIN_DT_DIG 0 VALUE={IF( ( ((V(HIN_DT_PLS) > 0.5) & (V(LOFF) > {P_TH_UP})) | {HB_EN} < 0.5 ) & (V(HIN_DD) > 0.5 ) & V( ++ VCC_UV) > 0.5 & V(SD_DD)>0.5 , 1.0 , 0.0 )} +E_LDT_PLS LIN_DT_PLS 0 VALUE={IF( ((V(LIN_DD) - V(HIN_DD)) > 0.1) | (V(LIN_DT_DIG) > 0.5) | ({HB_EN} < 0.5) , 1.0 , 0.0 )} +E_LIN_DT LIN_DT_DIG 0 VALUE={IF( ( ((V(LIN_DT_PLS) > 0.5) & (V(HOFF) > {P_TH_UP})) | {HB_EN} < 0.5 ) & (V(LIN_DD) > 0.5 ) , 1.0 , ++ 0.0 )} +E_SHT_H SHT_H 0 VALUE={IF( {SHT_EN} > 0.5 , V(HIN_DD) , V(HIN_DT_DIG) )} +E_SHT_L SHT_L 0 VALUE={IF( {SHT_EN} > 0.5 , V(LIN_DD) , V(LIN_DT_DIG) )} +G_H_DT VCC_1V HOFF VALUE={TABLE( V(VCC_1V,HOFF) , 0,0 , 10M, I_DT( V(DT,COM) ) )} +C_H_DT HOFF 0 {P_C_DT} +R_H_DT HOFF 0 1E8 +S_H_DT HOFF 0 SHT_H 0 IR2104S_DT_SW +G_L_DT VCC_1V LOFF VALUE={TABLE( V(VCC_1V,LOFF) , 0,0 , 10M, I_DT( V(DT,COM) ) )} +C_L_DT LOFF 0 {P_C_DT} +R_L_DT LOFF 0 1E8 +S_L_DT LOFF 0 SHT_L 0 IR2104S_DT_SW +.FUNC I_DT(V_DT) {{P_C_DT} * {P_TH_UP} / ({P_SLOPE_DT}/{P_I_DT}*V_DT + {P_OFFSET_DT})} +.MODEL IR2104S_DT_SW VSWITCH RON=1 ROFF=100MEG VON=0.8 VOFF=0.2 +.ENDS IR2104S_DEADTIME +.SUBCKT IR2104S_HO_STAGE HO HIN_DT_DIG VCC_UV VB_UV SD_DD VB VS PARAMS: P_RBOND_NMOS=10M P_RBOND_PMOS=10M P_C_GATE=1E-12 ++ P_HO_VGS_PMOS=6 P_HPMOS_LAMDA=0.06 P_HPMOS_KP=60U P_HO_VGS_NMOS=6 P_HNMOS_LAMDA=0.05 P_HNMOS_KP=100U +R_HIN_DT_DD HIN_DT_DIG HIN_DT_DD 100 +C_HIN_DT_DD HIN_DT_DD 0 1N +E_HIN_PLS HIN_PLS 0 VALUE {IF( (V(HIN_DT_DIG) - V(HIN_DT_DD)) > 0.1 | ((V(HGATE_DIG) > 0.5) & V(HIN_DT_DIG)>0.5), 1.0,0.0 )} +E_HGATE_DIG HGATE_DIG 0 VALUE {IF( ( V(HIN_PLS) > 0.5 & V(SD_DD) > 0.5 ) , 1.0,0.0 )} +R_HGATE HGATE_DIG HGATE 1 +C_HGATE HGATE 0 {P_C_GATE} +E_HGATE_P VB HGATE_P VALUE {V(HGATE) * {P_HO_VGS_PMOS} * V(HGATE_DIG)} +E_HGATE_N HGATE_N VS VALUE {(1 - V(HGATE)) * {P_HO_VGS_NMOS} * (1 - V(HGATE_DIG))} +M_HO_PMOS HO HGATE_P VB VB IR2104S_HO_PMOS +M_HO_NMOS HO HGATE_N VS VS IR2104S_HO_NMOS +.MODEL IR2104S_HO_PMOS PMOS (LEVEL=1 VTO=-1 CGSO=100P W=1M L=1U RB=1 RG=10 RS=10M RD={P_RBOND_PMOS} LAMBDA={P_HPMOS_LAMDA} KP= ++ {P_HPMOS_KP} ) +.MODEL IR2104S_HO_NMOS NMOS (LEVEL=1 VTO=1 CGSO=100P W=1M L=1U RB=1 RG=10 RS=10M RD={P_RBOND_NMOS} LAMBDA={P_HNMOS_LAMDA} KP= ++ {P_HNMOS_KP} ) +.ENDS IR2104S_HO_STAGE +.SUBCKT IR2104S_LO_STAGE LO LIN_DT_DIG VCC_UV SD_DD VCC COM PARAMS: P_RBOND_NMOS=10M P_RBOND_PMOS=10M P_C_GATE=1E-12 P_LO_VGS_PMOS= ++ 6 P_LPMOS_LAMDA=0.06 P_LPMOS_KP=60U P_LO_VGS_NMOS=6 P_LNMOS_LAMDA=0.05 P_LNMOS_KP=100U +E_LGATE_DIG LGATE_DIG 0 VALUE {IF( (V(VCC_UV) > 0.5 & V(LIN_DT_DIG) > 0.5 & V(SD_DD) > 0.5 ), 1.0,0.0 )} +R_LGATE LGATE_DIG LGATE 1 +C_LGATE LGATE 0 {P_C_GATE} +E_LGATE_P VCC LGATE_P VALUE {V(LGATE) * {P_LO_VGS_PMOS} * V(LGATE_DIG)} +E_LGATE_N LGATE_N COM VALUE {(1 - V(LGATE)) * {P_LO_VGS_NMOS} * (1 - V(LGATE_DIG))} +M_LO_PMOS LO LGATE_P VCC VCC IR2104S_LO_PMOS +M_LO_NMOS LO LGATE_N COM COM IR2104S_LO_NMOS +.MODEL IR2104S_LO_PMOS PMOS (LEVEL=1 VTO=-1 CGSO=100P W=1M L=1U RB=1 RG=10 RS=10M RD={P_RBOND_PMOS} LAMBDA={P_LPMOS_LAMDA} KP= ++ {P_LPMOS_KP} ) +.MODEL IR2104S_LO_NMOS NMOS (LEVEL=1 VTO=1 CGSO=100P W=1M L=1U RB=1 RG=10 RS=10M RD={P_RBOND_NMOS} LAMBDA={P_LNMOS_LAMDA} KP= ++ {P_LNMOS_KP} ) +.ENDS IR2104S_LO_STAGE +.SUBCKT IR2104S_UV_DETECT VCC_UV VB_UV VCC VB COM VS PARAMS: P_VB_UVL=7 P_VB_UVH=8 P_R_UV_D_H=142857 P_VCC_UVL=8 P_VCC_UVH=9 ++ P_R_UV_D_L=71428 +X_VB_UV VB VB_UV_DIG VS IR2104S_STP_IDEAL PARAMS: P_TH_UP={P_VB_UVH} P_TH_DW={P_VB_UVL} +E_VB_UVL VB_UVL 0 VALUE {IF( V(VB,VS) < {P_VB_UVL} , 0.0 , 1.0 )} +R_VB_UVL VB_UVL VB_UVL_LPF {P_R_UV_D_H} +C_VB_UVL VB_UVL_LPF 0 1P +E_VB_UVL_PLS VB_UVL_PLS 0 VALUE {IF( V(VB_UVL_LPF) < 0.5 | V(VB_UV) < 0.5 , 0.0 , 1.0 )} +E_VB_UV VB_UV 0 VALUE {IF( V(VB_UV_DIG) < 0.5 & V(VB_UVL_PLS) < 0.5 , 0.0 , 1.0 )} +X_VCC_UV VCC VCC_UV_DIG COM IR2104S_STP_IDEAL PARAMS: P_TH_UP={P_VCC_UVH} P_TH_DW={P_VCC_UVL} +E_VCC_UVL VCC_UVL 0 VALUE {IF( V(VCC,COM) < {P_VCC_UVL} , 0.0 , 1.0 )} +R_VCC_UVL VCC_UVL VCC_UVL_LPF {P_R_UV_D_L} +C_VCC_UVL VCC_UVL_LPF 0 1P +E_VCC_UVL_PLS VCC_UVL_PLS 0 VALUE {IF( V(VCC_UVL_LPF) < 0.5 | V(VCC_UV) < 0.5 , 0.0 , 1.0 )} +E_VCC_UV VCC_UV 0 VALUE {IF( V(VCC_UV_DIG) < 0.5 & V(VCC_UVL_PLS) < 0.5 , 0.0 , 1.0 )} +.ENDS IR2104S_UV_DETECT +.SUBCKT IR2104S_CC_EMULATOR VCC COM VB VS PARAMS: P_VB_MIN=10 P_VCC_MIN=10 P_IQ_VB_MIN=100U P_IQ_VCC_MIN=500U P_I_LEAK=1.0U ++ P_V_LEAK=650 P_VB_MAX=10 P_VCC_MAX=10 P_IQ_VB_MAX=100U P_IQ_VCC_MAX=500U +G_QB VB VS VALUE {TABLE(V(VB,VS) , 0,0 , 0.1,1U , 1,10U , {P_VB_MIN},{P_IQ_VB_MIN} , {P_VB_MAX},{P_IQ_VB_MAX} )} +R_QB VB VS 1E12 +G_QCC VCC COM VALUE {TABLE(V(VCC,COM) , 0,0 , 0.1,1U , 1,10U , {P_VCC_MIN},{P_IQ_VCC_MIN} , {P_VCC_MAX},{P_IQ_VCC_MAX} )} +R_QCC VCC COM 1E12 +G_VB_LEAK VS COM VALUE {TABLE(V(VB,COM) , 0,0 , {P_V_LEAK},{P_I_LEAK})} +R_VB_LEAK VS COM 1E12 +.ENDS IR2104S_CC_EMULATOR +.SUBCKT IR2104S_CL_DIO C A PARAMS: P_V_BV=5 P_I_BV=1 +G_CL_DIO C A VALUE {TABLE(V(C,A) , 0,0 , {P_V_BV}*1.01,0 , {P_V_BV}*1.02,{P_I_BV} , 10*{P_V_BV}, 100*{P_I_BV} )} +C_CL_DIO C A 10F +R_CL_DIO C A 1E12 +.ENDS IR2104S_CL_DIO +.SUBCKT IR2104S_ESD_DIO A C PARAMS: P_V_BV=5 P_I_BV=1 +G_ESD_DIO A C VALUE {TABLE(V(A,C) , 0,0 , {P_V_BV}*1.01,0 , {P_V_BV}*1.02,{P_I_BV} , 10*{P_V_BV}, 100*{P_I_BV} )} +C_ESD_DIO A C 10F +R_ESD_DIO A C 1E12 +.ENDS IR2104S_ESD_DIO +.SUBCKT IR2104S_RC_DELAY_10 IN OUT PARAMS: P_C_DELAY = 60E-9 P_TH_TPD = 0.5 +X_D1 IN D1 IR2104S_RC_DELAY_5 PARAMS: P_C_DELAY = {P_C_DELAY} P_TH_TPD = {P_TH_TPD} +X_D2 D1 OUT IR2104S_RC_DELAY_5 PARAMS: P_C_DELAY = {P_C_DELAY} P_TH_TPD = {P_TH_TPD} +.ENDS IR2104S_RC_DELAY_10 +.SUBCKT IR2104S_RC_DELAY_5 IN OUT PARAMS: P_C_DELAY = 60E-9 P_TH_TPD = 0.5 +X_D1 IN D1 IR2104S_RC_DELAY_BASE PARAMS: P_C_DELAY = {P_C_DELAY} P_TH_TPD = {P_TH_TPD} +X_D2 D1 D2 IR2104S_RC_DELAY_BASE PARAMS: P_C_DELAY = {P_C_DELAY} P_TH_TPD = {P_TH_TPD} +X_D3 D2 D3 IR2104S_RC_DELAY_BASE PARAMS: P_C_DELAY = {P_C_DELAY} P_TH_TPD = {P_TH_TPD} +X_D4 D3 D4 IR2104S_RC_DELAY_BASE PARAMS: P_C_DELAY = {P_C_DELAY} P_TH_TPD = {P_TH_TPD} +X_D5 D4 OUT IR2104S_RC_DELAY_BASE PARAMS: P_C_DELAY = {P_C_DELAY} P_TH_TPD = {P_TH_TPD} +.ENDS IR2104S_RC_DELAY_5 +.SUBCKT IR2104S_RC_DELAY_BASE IN OUT PARAMS: P_C_DELAY = 60E-9 P_TH_TPD = 0.5 +R_DELAY IN IN_DEL 1 +C_DELAY IN_DEL 0 {P_C_DELAY} +E_DELAY OUT 0 VALUE={IF( V(IN_DEL) > {P_TH_TPD} , 1.0,0.0 )} +.ENDS IR2104S_RC_DELAY_BASE +.SUBCKT IR2104S_ADV_FILTER IN OUT PARAMS: P_C_DELAY = 60E-9 P_TH_TPD = 0.5 +R_RISE IN IN_DEL 1 +C_RISE IN_DEL 0 {P_C_DELAY} +X_CMP IN_DEL OUT 0 IR2104S_STP_IDEAL PARAMS: P_TH_UP=0.999 P_TH_DW=0.001 +.ENDS IR2104S_ADV_FILTER +.SUBCKT IR2104S_STP_IDEAL IN OUT GND PARAMS: P_TH_UP=0.9 P_TH_DW=0.1 +E_OUTP OUTP 0 VALUE={IF( V(IN,GND)>={P_TH_UP} | V(OUTN)<0.5 , 1,0 )} +E_OUTN OUTN 0 VALUE={IF( V(IN,GND)<={P_TH_DW} | V(OUTP)<0.5 , 1,0 )} +E_OUT OUT 0 VALUE={V(OUTP)} +.ENDS IR2104S_STP_IDEAL +.SUBCKT IR2104S_STN_IDEAL IN OUT GND PARAMS: P_TH_UP=0.9 P_TH_DW=0.1 +E_OUTP OUTP 0 VALUE={IF( V(IN,GND)>={P_TH_UP} | V(OUTN)<0.5 , 1,0 )} +E_OUTN OUTN 0 VALUE={IF( V(IN,GND)<={P_TH_DW} | V(OUTP)<0.5 , 1,0 )} +E_OUT OUT 0 VALUE={V(OUTN)} +.ENDS IR2104S_STN_IDEAL \ No newline at end of file diff --git a/DCC-Booster-Endstufe/Screenshot.png b/DCC-Booster-Endstufe/Screenshot.png new file mode 100644 index 0000000..cf47b19 Binary files /dev/null and b/DCC-Booster-Endstufe/Screenshot.png differ