Test mit kapazitiver, induktiver und ohmscher Last.

main
Tom 11 months ago
parent d7fc77f527
commit 930aca618e

6
.gitattributes vendored

@ -0,0 +1,6 @@
*.asc linguist-language=LTSpice
*.log linguist-language=Log
*.asy linguist-language=LTSpice
*.lib linguist-language=LTSpice
*.raw linguist-language=LTSpice
*.plt linguist-language=LTSpice

@ -29,6 +29,8 @@ WIRE -416 0 -464 0
WIRE -240 0 -240 -112
WIRE -240 0 -288 0
WIRE 192 16 192 -480
WIRE 432 16 400 16
WIRE 512 16 496 16
WIRE 752 16 752 -480
WIRE 1264 16 1216 16
WIRE 1456 16 1392 16
@ -57,6 +59,10 @@ WIRE -64 96 -96 96
WIRE 32 96 32 32
WIRE 32 96 16 96
WIRE 144 96 32 96
WIRE 400 96 400 16
WIRE 416 96 400 96
WIRE 512 96 512 16
WIRE 512 96 496 96
WIRE 656 96 656 -80
WIRE 704 96 656 96
WIRE 1264 112 1232 112
@ -68,10 +74,10 @@ WIRE -176 160 -176 64
WIRE 192 160 192 112
WIRE 192 160 -176 160
WIRE 304 160 192 160
WIRE 400 160 400 16
WIRE 400 160 400 96
WIRE 400 160 304 160
WIRE 416 160 400 160
WIRE 512 160 512 16
WIRE 512 160 512 96
WIRE 512 160 496 160
WIRE 592 160 512 160
WIRE 752 160 752 112
@ -242,17 +248,27 @@ SYMATTR InstName V4
SYMATTR Value 5V
SYMBOL cap 384 224 R0
SYMATTR InstName C3
SYMATTR Value 100n
SYMATTR Value 47n
SYMBOL cap 496 224 R0
SYMATTR InstName C4
SYMATTR Value 100n
SYMATTR Value 47n
SYMBOL Digital\\inv -320 416 R0
WINDOW 3 12 105 Left 2
SYMATTR Value Vhigh=5 Vlow=1
SYMATTR InstName A1
SYMBOL ind 512 80 R90
WINDOW 0 5 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName L1
SYMATTR Value 100ľH
SYMBOL cap 496 0 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C5
SYMATTR Value 100pF
TEXT -936 456 Left 2 !.tran 500µs
TEXT -184 -400 Left 2 ;Netzteil Gleisspannung
TEXT -920 -592 Left 2 ;_SD Gate Driver Enable (Port vom Controller)
TEXT -440 -544 Left 2 ;+12V VCC Gate Driver
TEXT -1008 496 Left 2 ;PWM Generator 58µs / 116µs DCC Signal
TEXT 408 40 Left 4 ;Gleis
TEXT 408 -48 Left 4 ;Gleis

@ -23,12 +23,14 @@ vernier = 0.03125
vernier = 0.015625
vernier = 0.0078125
vernier = 0.00390625
Gmin = 1.00079
vernier = 0.00195313
vernier = 0.000976563
Gmin = 1.00226
vernier = 0.00260417
vernier = 0.00130208
vernier = 0.000651042
Gmin = 0.999977
vernier = 0.000488281
Gmin = 0
Gmin = 0
Gmin stepping failed
Starting source stepping with srcstepmethod=0
@ -53,39 +55,39 @@ Changing Tseed to 4.88281e-013
Changing Tseed to 4.88281e-008
Changing Tseed to 4.88281e-014
to 5.49316e-014
Heightened Def Con from 7.97822e-007 to 7.98697e-007
Heightened Def Con from 5.85043e-005 to 5.85062e-005
Heightened Def Con from 5.9027e-005 to 5.90278e-005
Heightened Def Con from 0.000116278 to 0.000116279
Heightened Def Con from 0.000116796 to 0.000116797
Heightened Def Con from 0.000174513 to 0.000174515
Heightened Def Con from 0.000175037 to 0.000175038
Heightened Def Con from 0.000232265 to 0.000232266
Heightened Def Con from 0.000232786 to 0.000232787
Heightened Def Con from 0.000290519 to 0.000290521
Heightened Def Con from 0.000291036 to 0.000291036
Heightened Def Con from 0.000348263 to 0.000348264
Heightened Def Con from 0.000348768 to 0.000348769
Heightened Def Con from 0.000406519 to 0.000406521
Heightened Def Con from 0.000407043 to 0.000407043
Heightened Def Con from 0.000464275 to 0.000464276
Heightened Def Con from 0.000464794 to 0.000464795
Heightened Def Con from 6.71545e-007 to 6.7242e-007
Heightened Def Con from 7.96492e-007 to 7.97367e-007
Heightened Def Con from 5.85119e-005 to 5.85138e-005
Heightened Def Con from 5.90347e-005 to 5.90355e-005
Heightened Def Con from 0.000116248 to 0.000116248
Heightened Def Con from 0.000116772 to 0.000116773
Heightened Def Con from 0.000174531 to 0.000174532
Heightened Def Con from 0.00017505 to 0.000175051
Heightened Def Con from 0.000232263 to 0.000232263
Heightened Def Con from 0.000232775 to 0.000232776
Heightened Def Con from 0.000290504 to 0.000290506
Heightened Def Con from 0.000291024 to 0.000291025
Heightened Def Con from 0.000348266 to 0.000348266
Heightened Def Con from 0.00034878 to 0.000348781
Heightened Def Con from 0.000406497 to 0.000406499
Heightened Def Con from 0.000407016 to 0.000407017
Heightened Def Con from 0.000464263 to 0.000464263
Date: Sun Mar 26 11:18:34 2023
Total elapsed time: 4.092 seconds.
Date: Sun Mar 26 13:00:37 2023
Total elapsed time: 3.548 seconds.
tnom = 27
temp = 27
method = modified trap
totiter = 49817
traniter = 31481
tranpoints = 9771
accept = 6953
rejected = 3198
totiter = 51573
traniter = 33169
tranpoints = 9930
accept = 7079
rejected = 3231
matrix size = 577
fillins = 267
fillins = 271
solver = Normal
Thread vector: 29.7/13.5[16] 8.0/2.5[16] 21.1/3.2[16] 0.9/1.5[1] 2592/500
Matrix Compiler1: 30.76 KB object code size 5.9/3.1/[1.5]
Matrix Compiler2: 41.67 KB object code size 3.2/5.3/[1.4]
Thread vector: 46.0/11.5[16] 7.9/3.0[16] 22.6/3.1[16] 0.9/1.6[1] 2592/500
Matrix Compiler1: 31.00 KB object code size 6.0/3.1/[1.5]
Matrix Compiler2: 41.75 KB object code size 4.1/5.8/[1.4]

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